To demonstrate this, the following is the eight steps needed to create a new document type for the Verilog language.
Step 1: Use the Options, Document Types menu to bring up the document type dialog and use the New button to create a new document type.
Step 2: In the General panel enter the following data:
- v as the file extension
- Verilog Document Type as the description
- ^module as the function regexp (regular expression)
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always
and
assign
attribute
begin
buf
bufif0
bufif1
case
none
casez
cmos
deassign
default
defparam
defpram
disable
edge
else
end
endattribute
endcase
endfunction
endfunction
endmodule
endmodule
endprimitive
endspecify
endtable
endtask
event
for
force
forever
fork
function
highz0
highz1
if
ifnone
initial
inout
input
integer
join
large
macromodule
medium
module
nand
negedge
nmos
nor
not
notif0
notif1
or
output
parameter
pmos
posedge
primitive
pull0
pull1
pulldown
pullup
rcmos
real
realtime
reg
release
repeat
rnmos
rpmos
rtran
rtranif0
rtranif1
scalared
signed
small
specify
specparam
specpram
strength
strong0
strong1
supply0
supply1
table
task
time
tran
tranif0
tranif1
tri
tri0
tri1
triand
trior
trireg
unsigned
vectored
wait
wand
weak0
weak1
while
wire
wor
xnor
xor
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$async$and$array
$async$and$plane
$async$nand$array
$async$nand$plane
$async$nor$array
$async$nor$plane
$async$or$array
$async$or$plane
$bitstoreal
$comment
$date
$display
$displayb
$displayh
$displayo
$dist_chi_square
$dist_erlang
$dist_exponential
$dist_nornal
$dist_poisson
$dist_t
$dist_uniform
$dumpall
$dumpoff
$dumpon
$dumpvars
$enddefinitions
$fclose
$fdisplay
$fdisplayb
$fdisplayh
$fdisplayo
$finish
$fmonitor
$fmonitorb
$fmonitorh
$fmonitoro
$fopen
$fstrobe
$fstrobeb
$fstrobeh
$fstrobeo
$fwrite
$fwriteb
$fwriteh
$fwriteo
$hold
$itor
$monitor
$monitorb
$monitorh
$monitoro
$monitoroff
$monitoron
$nochange
$period
$printtimescale
$q_add
$q_exam
$q_full
$q_initialize
$q_random
$q_remove
$random
$readmemb
$readmemh
$readtobits
$realtime
$recovery
$rtoi
$scope
$setup
$setuphold
$skew
$stime
$stop
$strobe
$strobeb
$strobeh
$strobeo
$sync$and$array
$sync$and$plane
$sync$nand$array
$sync$nand$plane
$sync$nor$array
$sync$nor$plane
$sync$or$array
$sync$or$plane
$time
$timeformat
$timescale
$upscope
$var
$version
$width
$write
$writeb
$writeh
$writeo
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celldefine
default_nettype
define
delay_mode_distributed
delay_mode_path
delay_mode_unit
delay_mode_zero
else
endcelldefine
endif
ifdef
include
nounconnected_drive
reset_all
resetall
timescale
unconnected_drive
undef
uselib
- " as the string characters (ie a single double quote)
- /* as comment start
- */ as comment end
- // as line comment 1
- %?,:;<>{}[]()*+/-=|&!^~.'@ as delimiters
- ([0-9]+'[0-9a-zA-Z]+)|([0-9.]+([eE]*)) as numbers
- Import c:\temp\v1.txt to the reserved words list
- Import c:\temp\v2.txt to the user defined words list 1
- Import c:\temp\v3.txt to the user defined words list 2
Step 6: Apply the changes and open a Verilog file. If the colors need fine tuning use the Options, Color Options menu to bring up the color settings and adjust the colors to taste.
Step 7: Change to the Templates panel and enter begin and end as the Brace Prefix and Brace Postfix strings.
Step 8: Use the Compiler panel to define a compiler command line string.
If this new language is a scripting language refer to document type of one of the other scripting languages like Python or Lua for an example of what to do in this panel.
If this is a statically typed language then refer to the C/C++ or C# document type for help.
To get the ctags to work for the language go here for more details.