Zeus IDE

Posted: **Thu Sep 29, 2016 4:11 pm**

I'm trying to get the editor to do autocomplete and I'm having zero luck. I can't get the real-time to work at all no matter when I type '.' so I must be missing something basic. If I use the manual "tags -> Autocomplete current word..." it pops works for some.

Which leads me to my next question - I'm using this for Verilog and it's not picking up the variable names - just the top level modules. How do I get it to do that?

Any info greatly appreciated. Thanks-

Posted: **Fri Sep 30, 2016 12:06 am**

Since the completion works manually for some, but not automatically suggests to me this sounds like a bug in Zeus

Now I also suspect this should be a fairly easy bug to fix, but to get this fixed I will need some help from you.

What I would need is a simple one file example of Verilog code containing typical examples auto-completions you would expect to see working.

The code does not need to compile, it just needs to contain those code snippets that should auto-complete.

If you can post that file here as an attachment or send it to me as e-mail that would be great.

With that code it should be fairly easy to figure out at this end why this is not working

Cheers Jussi

Posted: **Fri Sep 30, 2016 9:07 am**

I had a quick look at this auto-complete issue.

What I found was this snippet of code does not autocomplete:

Code: Select all

primitive prim_input (c,a,b);
      output c;
endprimitive

But this one does autocomplete:

Code: Select all

function func_input (c,a,b);
      output c;
endfunction

The reason for the difference is the first example is not identified by the ctags tool where as the second one is.

I suspect the error you are seeing is probably a similar issue relating to the information generated by the ctags tool.

To fix these sort of ctags issues requires simple code examples, just like the ones shown above.

Cheers Jussi

Posted: **Sat Oct 01, 2016 3:42 am**

Here is a simple test case I was trying -

Code: Select all

module MAX10_ST (
output reg [7:0] dout,
input wire rst_n,
input wire clk
);

reg [7:0] din ;
wire clk_int ;

always @ (posedge clk or negedge rst_n)
begin
if (~rst_n) dout <= `DELAY 8'h00 ;
else dout <= `DELAY dout + 1 ;
end //always
endmodule

If I type "MAX" then Ctrl-F1, it gives the autocomplete option of "MAX10_ST"
If I type "cl" then Ctrl-F1, it gives the autocomplete option of "clk_int" but not "clk"
If I type "rst" then Ctrl-F1, I would expect the option of "rst_n", but I get nothing.

All this is manual. If I try "automatic" by typing '.' I get nothing
If I type "MAX." I get nothing.
If I type ".MAX" I also get nothing.

I'm assuming one of those should have triggered the auto-complete. Any insight greatly appreciated. Thanks

Posted: **Sat Oct 01, 2016 9:51 am**

The main reason this is not working was because, as suspected the ctags.exe is not generating the correct tags information.

I found an alternative ctags tool here: https://github.com/universal-ctags/ctags

Building that tool creates this alternative xtags.exe executable: http://www.zeusedit.com/z300/xtags.zip

So you need replace the xtags.exe found in the C:\Program Files (x86)\Zeus\ folder with the one from the download link above.

If I type "MAX" then Ctrl-F1, it gives the autocomplete option of "MAX10_ST"
If I type "cl" then Ctrl-F1, it gives the autocomplete option of "clk_int" but not "clk"
If I type "rst" then Ctrl-F1, I would expect the option of "rst_n", but I get nothing.

With that new xtags.exe these should be fixed.

All this is manual. If I try "automatic" by typing '.' I get nothing
If I type "MAX." I get nothing.
If I type ".MAX" I also get nothing.

I'm not sure what you mean by this

The way the '.' works is defined by languages like C++, C#. Python etc and for it to work you need some sort of class construct.

Here is an simple example:

Code: Select all

class Example
{
public:
        int a;
        int b;
}

This would then allow the '.' to intellisense in code like this:

Code: Select all

    Example test;

    test.   << the autocomplete will display a and b as options

But for the Verilog example you have provided, the tags information does not contain any such class information.

Cheers Jussi

Zeus IDE

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