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Verilog BraceMatch
Posted: Tue May 10, 2005 2:41 am
by banjo
Is it possible to add to the BraceMatch list? Verilog uses the words "begin" and "end". Most editors cannot handle these for "matching the braces".
Thanks.
--- Steve
Posted: Tue May 10, 2005 3:42 am
by Guest
Hi Steve,
To do this you need to do the following:
- Create a Verilog document type
- Change to the templates section of the document type
- Add begin to the brace prefix string
- Add end to the brace postfix string
- Apply the changes[/b]
Now if you have code that looks like something this:
Code: Select all
if something
begin
something else
end
placing the cursor on the
begin or
end words and using the
Edit Find Matching Brace should see the cursor move to the matching brace.
Also if you enter something like this:
hitting the enter key should see Zeus auto brace the code to look like this:
Code: Select all
if something
begin
<-- cursor now here
end
Finally, Zeus currently does not have support for Verilog code folding but if you create a
Verilog language specification this feature could also be added.
Cheers Jussi