Verilog Code Folding Description

This forum should be used for all code folding problems, questions or suggestions. You can also use this forum to request folding support for a new language.
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emh203@psu.edu

Verilog Code Folding Description

Post by emh203@psu.edu » Mon Jun 13, 2005 3:35 pm

Extension: .v
Line Comment: //
Block Comment: /* */
Begin: BEGIN
End: END

Sample Code:

module test(clk, enable, value)
input clk;
input enable;
output [7:0] value;

reg [7:0] count;

always @(posedge clk)
begin
if(enable == 0)
count <= 0;
else
count <=count + 1;
end

endmodule

jussij
Site Admin
Posts: 2508
Joined: Fri Aug 13, 2004 5:10 pm

Post by jussij » Tue Jun 14, 2005 9:30 am

The code folding for Verilog has been implemented and the new xFolder.dll can be found here:

http://www.zeusedit.com/z300/xfolder.zip

To install the new folding dll:
  1. Make a backup copy of the current xFolder.dll and replace it with xFolder.dll from the link above
  2. Create a Verilog Document Type.
  3. Open a Verilog file
  4. Turn on code folding using the View, Folding, Folding Margin menu.
NOTE: There is a limitation in the Zeus folding feature in that it never expects to see a end and a begin fold on the same line. To understand what this means consider this snippet of Verilog code:

Code: Select all

 if (~reset) begin
   q <= 1'b0;
 end else begin
   q <= data;
 end
This code will fold incorrectly because of the end else begin line. For the folding to work correctly the code needs to be re-formated as follows:

Code: Select all

 if (~reset) begin
   q <= 1'b0;
 end
 else
 begin
   q <= data;
 end

emh203@psu.edu

Post by emh203@psu.edu » Wed Jun 15, 2005 12:16 pm

Just tried it out and it works great! Thank you for the great response time. I have been looking for this feature for awhile. I will definately buy this software!!

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